Fully strain relaxed epitaxial SiGe on silicon (Si) has numerous potential applications for electrical and opto-electrical devices. For practical applications, the epitaxial layer must have a high degree of strain relaxation, a low threading dislocation density, as well as a smooth surface. In addition, the SiGe layer thickness must be minimized, because as SiGe layer thickness increases, production costs rise and significant technological issues occur, such as poor thermal conductivity associated with the SiGe. These requirements are often self-contradictory according to experimental results and theoretical modeling. For example, both experimental results and theoretical models demonstrate that the strain relaxation degree for SiGe on Si depends on SiGe layer thickness—the thicker the layer, the higher the strain relaxation degree. A high degree of strain relaxation (on the order of 90%) is expected only for very thick films (e.g., 2 micrometers for SiGe with 20% Ge), but is not practical in terms of cost. Similarly, the threading dislocation density (TDD) is shown as a function of the SiGe film thickness, whereby TDD decreases with increasing epitaxial layer thickness. As a result, it is a challenge to manufacture thin SiGe (less than 200 nm) on Si with a high degree of strain relaxation and low TDD for device applications.
One conventional approach employs compositionally graded buffers, in which very thick buffers (several micrometers) are grown on a Si substrate with Ge composition increasing from the Si substrate to the buffer surface. FIG. 1A illustrates a semiconductor device including a Si substrate 101, a reverse-graded SiGe buffer layer 103, and a relaxed SiGe epitaxial layer 105. FIG. 1B shows an example of the respective atomic concentration of the Si and Ge at different depths of the semiconductor device. The reverse-graded SiGe buffer layer 103 may be grown to 100 nm to 300 nm in thickness, but requires a low temperature (e.g., 400° C.), which is difficult to implement practically, because there is no appreciable Si growth using normal Si hydride sources such as SiH4 and Si2H6 at that temperature for standard chemical vapor deposition (CVD) epitaxial reactors.
Another conventional approach involves the growth of a thin SiGe layer on top of alternating SiGe/SiGeC buffer layers. FIG. 2 illustrates a semiconductor device including a Si substrate 201, a SiGeC layer 203, SiGe layer 205, a SiGeC layer 207, SiGe layer 209, and a relaxed SiGe epitaxial layer 211. According to this approach, a thin SiGe epitaxial layer 211 can be grown on Si, having a low TDD, but a SiGeC layer grown with high Ge % and high C % is challenging for volume manufacturing.
A need therefore exists for methodology enabling manufacture of a strain relaxed epitaxial SiGe layer with a high strain relaxation degree, a low TDD, and a reduced layer thickness that is viable for volume production, and the resulting semiconductor devices.